主办单位：国家集成电路设计北京产业化基地
承办单位：冠讯科技（上海）有限公司

开课时间： 2003年8月21日
报名地点：北京市海淀区知春路27号北京集成电路设计园培训中心
主讲教师： Synplicity 资深工程师
培训费用： RMB500.00/人 （包括工作午餐、教材、上机费用）
培训对象：Designers who wish to create successful FPGA-based prototypes of their ASIC 　　　　　　designs utilizing the Certify product and debug with Identify.
学员要求：Familiarity with prototyping issues and experience in Verilog or VHDL design 　　　　　and synthesis.

　Course Overview

　　This course introduces concepts on ASIC prototyping using the Certify ASIC 　　　　　　Prototyping tool. The focus will be on understanding concepts on RT-level 　　　　　　　partitioning, using the Certify product to create a successfully partitioned design, 　　and debug prototyping with Identify.

　Students Will Learn:
　　o Certify Product Concepts
　　o Understanding the Certify UI
　　o Specification of Prototype Board Descriptions
　　o Partitioning to FPGA Devices
　　o Identify Instrumentor
　　o How to debug with Identify Debugger

　Course Description

　　This course introduces the new user to the Certify ASIC Prototyping tool. The course 　　will familiarize the student with the ASIC prototype design flow utilizing features 　　of the Certify product, enabling the student to actively partition an ASIC design 　　　without changes to the RTL source.

　Topics Covered Include:

　　o Project Management
　　o RTL Prototyping Concepts
　　o Defining a Board Description File
　　o Advanced Partitioning Tools
　　o Area Estimation
　　o Creating a Successful Partition
　　o Hierarchical Systems
　　o Debug Insertion Features
　　o Performing Pin Assignment
　　o Instrument and debug data path
　　o Instrument and debug control path

　Benefit
　　Through the design experience of Synplicity Corporate Application Engineers, 　　　　　students will learn to use the powerful features of the Certify product in their 　　　prototype solutions, including the ability to partition and debug an ASIC design 　　　description and create a high-performance, FPGA-based prototype.