1

Cadence(R) NC-Verilog(R) Simulator

2

Cadence(R) NC-VHDL Simulator

3

Incisive Enterprise Specman Elite

4

Verifault(R)-XL simulator

1

Encounter RTL Compiler -L

1

SE PKS optimization place-and-route

SE ultra

PKS concurrent optimization

SI prevention and correction capabilities

2

Envisia place-and-route clock tree generator

3

Soc Encounter

1

Encounter (TM) Conformal - L (a.k.a Conformal ASIC)

1

Dracula physical verification and parasitic extraction suite

Dracula(R) design rule checker

Dracula(R) layout vs. schematic verifier

Dracula(R)parasitic extraction

2

Assura(TM) Design Rule Checker

3

Assura(TM) Layout Vs. Schematic Verifier

4

Assura(TM) Parasitic Extractor

1

Virtuoso(R) Schematic Editor -L

2

Virtuoso layout editor

3

Virtuoso(R) Layout Editor Turbo

4

Virtuoso(R) Analog Design Environment -L

5

Virtuoso(R) Spectre(R) Circuit Simulator

6

Virtuoso(R) Spectre(R)-RF Simulation Option

7

Virtuoso stream interface

1

Signal processing worksystem 2000

2

Floating point communication library

3

Fixed point communication library

4

Hardware design system 2000

5

Wideband  CDMA library

6

Wireless local area network library

7

Multimedia design kit

8

GSM verification environment

9

SPW link to NC-simulator