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“
TetraMAX® 1
”
培训课程
北京集成电路设计园与Synopsys公司将于2007年3月15日-16日举办“TetraMAX®
1”培训课程，以帮助IC工程师进一步全面系统地理解IC设计概念与方法。培训将采用Synopsys公司相关领域的培训教材，并由Synopsys公司资深工程师主讲，培训方式以讲课和实验穿插进行，保证一人一机及足够的上机时间，并按要求完成所有的实验操作，培训结束颁发培训证书。
以下是课程介绍：
TetraMAX® 1
OVERVIEW
In this two-day workshop, you will learn how use
TetraMAX®--Synopsys' ATPG Tool for SOC design--to perform the
following tasks:
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Generate test patterns for stuck-at faults given a scan
gate-level design created by DFT Compiler or other tools
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Describe the test protocol and test pattern timing using STIL
-
Debug DRC and stuck-at fault coverage problems using the
Graphical Schematic Viewer
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Troubleshoot fault coverage problems
-
Save and validate test patterns
This class does NOT cover the fundamentals of manufacturing test,
such as:
-
What is manufacturing test?
-
Why perform manufacturing test?
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What is a stuck-at fault?
-
What is a scan chain?
This class introduces but does not cover in detail the DSMTest
option and the Failure Diagnosis feature of TetraMAX®.
This class does not cover in detail the DSMTest option to TetraMAX®
or the Scan Failure Diagnosis or the fundamentals of manufacturing
test.
OBJECTIVES
At the end of this workshop the student should be able to:
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Incorporate TetraMAX® ATPG in a design and test methodology that
produces desired fault coverage, ATPG vector count and ATPG
run-time for a full-scan or almost full-scan design
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Create a STIL Test Protocol File for a design by using QuickSTIL
menus or commands, DFT Compiler or from scratch
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Use the Graphical Schematic Viewer to analyze and debug warning
messages from Design Rule Check or fault coverage problems after
ATPG
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Customize a Test Protocol for a design that requires special
circuit initialization, scan shift or capture procedures or
pattern timing
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Describe when and how to use at least four options to increase
test coverage and/or decrease the number of required test
patterns
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Save test patterns in a proper format for simulation and
transfer to an ATE
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Validate test patterns using STIL Direct Pattern Validation
AUDIENCE PROFILE
ASIC, SoC or Test Engineers who perform ATPG at the Chip or SoC
level
PREREQUISITES
To benefit the most from the material presented in this workshop,
students should: Have taken the
DFT Compiler 1 workshop or possess equivalent knowledge with DFT
Compiler and fundamentals of manufacturing test including:
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Understanding the differences between manufacturing and design
verification testing
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Stuck-at fault model
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Internal and boundary scan chains
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Scan shift and capture violations
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Major scan design-for-test rules concerning flip-flops, latches
and bi-directional/tri-state drivers
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Tradeoffs between having single or multiple
-
Understanding of digital IC logic design
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Working knowledge of Verilog or VHDL language
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Familiarity with UNIX workstations running X-windows
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Familiarity with vi, emacs, or other UNIX text editors
Students should make sure they are fully prepared to take this
advanced material by conducting a self-assessment with the
TetraMAX® 1 Prerequisite Test.
COURSE OUTLINE
Day 1
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Introduction to ATPG Flow
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Building ATPG Models
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Running DRC
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Controlling ATPG
Day 2
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Minimizing ATPG Patterns
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Fault Simulation
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Writing ATPG Patterns
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Pattern Validation
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DSM Testing Challenges
SYNOPSYS TOOLS USED
TetraMAX® 2004.12
VCS version 7.2
讲
师：Synopsys公司资深工程师
培训时间：2007年3月15日—16日9：00—17：00
培训地点：北京市海淀区知春路27号量子芯座5层培训中心
培训费用：人民币800元/人/天（含培训费、实验费、教材费、午餐），参加系列培训可享受
优惠，采用现金、支票、汇款支付均可。
报名电话：82351166/87239511（移动）
传真：82357178
E－mail
：ictrain@bjicpark.com
网址：www.bjicpark.com
交费地点：北京市海淀区知春路27号量子芯座5层北京集成电路设计园培训中心
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请于开课前提前5个工作日将报名回执传真或Email至设计园，提前2个工作日将培训费用（现金、支票、汇款均可）交到设计园。
单位名称：北京集成电路设计园有限责任公司
开户银行：招商银行大运村支行
银行帐号：6381001510001
行 号：649
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