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“IC
compiler 1” 培训课程
北京集成电路设计园与Synopsys公司将于2007年10月10日-12日举办“IC
compiler 1”培训课程，以帮助IC工程师进一步全面系统地理解IC设计概念与方法。
以下是课程介绍：
OVERVIEW
The
workshop starts out with a high level introduction to IC Compiler’s
graphical user interface, during which you will learn about the 3
core commands, place_opt, clock_opt and route_opt as well as the
more targeted atomic commands for more specific needs.
You
will learn the details of design and timing setup, including setting
up all physical and logical libraries, importing various design
formats and floorplans, and setting the design up for proper timing
analysis.
The
workshop goes in-depth into using IC Compiler to perform placement,
power optimization, scan optimization, clock tree synthesis and
routing operations, including interleaved logic optimizations. You
will also learn how to perform Design for Manufacturing tasks in IC
Compiler, including antenna fixing, via doubling, metal filling and
critical area optimization.
Another unit is dedicated to the topic of the new Multi Scenario
capabilities, including how to apply SDC constraint files and
operating conditions and perform analysis and optimization in
parallel. The unit will also show you the advantages of using
on-chip variation mode.
The
class will explore the new Design Planning features in IC Compiler,
which support full flat floorplanning including automatic macro
placement, power network synthesis and analysis, and prototype route
and optimization.
The
workshop is accompanied by comprehensive hands-on labs, which
provide an opportunity to apply all concepts covered during the
lectures.
OBJECTIVES
At
the end of this workshop you should be able to:
Read
necessary files required to run IC Compiler, resolving common
errors/warnings Set up timing for analysis and optimizations Perform
placement and optimizations Analyze congestion maps and reports
Perform power optimization Perform scan reordering using ScanDEF Set
up the design for clock tree synthesis Perform clock tree synthesis
and post CTS optimizations
Analyze timing and clock specifications post CTS Route the design
using the core and atomic commands Describe the need for
Multi-corner, Multi-Mode analysis and optimization Specify a
scenario in IC Compiler Analyze the design for SI and perform SI
optimizations Perform unconstrained and freeze silicon ECOs Perform
antenna fixing, via doubling, metal filling, filler cell insertion,
critical area optimization Create a flat floorplan including core
and IO area setup, power network synthesis and routing, timing
driven macro placement Perform power network analysis and virtual
pad insertion
AUDIENCE PROFILE
ASIC,
back-end or layout designers with experience in standard cell-based
automatic Place and Route.
PREREQUISITES
To
benefit the most from the material presented in this workshop,
students should have working knowledge of Physical Design using
Physical Compiler, Astro, or any other Physical Design tool.
COURSE OUTLINE
Day 1
Introduction
IC
Compiler Basic Flow
Placement, Power andTest
Day 2
Clock
Tree Synthesis
Multi
Scenario Optimization
Day 3
Design Planning
Routing and Signal Integrity
Chip
Finishing and DFM
讲
师：Synopsys公司资深工程师
培训时间：2007年10月10日-12日9：00—17：00
培训地点：海淀区科学院南路2号融科资讯中心A座7层711室（新思科技公司）
培训费用：人民币800元/人/天（含培训费、实验费、教材费、午餐），参加系列培训可享受优惠，采用现金、支票、汇款支付均可。
报名电话：82351166/87239511（移动）
传真：82357178
E－mail
：ictrain@bjicpark.com
网址：www.bjicpark.com
交费地点：北京市海淀区知春路27号量子芯座5层北京集成电路设计园培训中心
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公司名称：
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请于开课前提前5个工作日将报名回执传真或Email至设计园，提前2个工作日将培训费用（现金、支票、汇款均可）交到设计园。
单位名称：北京集成电路设计园有限责任公司
开户银行：招商银行大运村支行
银行帐号：6381001510001
行 号：649
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