“ Design Compiler 1 ”  培训课程

   北京集成电路设计园与Synopsys公司将于2007年11月14日-16日举办“Design Compiler 1”培训课程，以帮助IC工程师进一步全面系统地理解IC设计概念与方法。培训将采用Synopsys公司相关领域的培训教材，并由Synopsys公司资深工程师主讲，培训方式以讲课和实验穿插进行，保证一人一机及足够的上机时间，并按要求完成所有的实验操作，培训结束颁发培训证书。

以下是课程介绍：

Design Compiler 1

OVERVIEW

This course covers the ASIC synthesis flow using Design Compiler -- from reading in an RTL design (Verilog and VHDL) to generating a final gate-level netlist. You will learn how to read in your design file(s), specify your libraries, constrain a complex design for area and timing, partition your design’s hierarchy for synthesis, apply synthesis techniques to achieve area and timing closure, analyze the synthesis results, and generate output data that works with downstream layout tools. The course includes labs to reinforce and practice key topics discussed in lecture. All the covered commands and flows are printed separately in a 3-page Job Aid which the student can refer to back at work.

OBJECTIVES

At the end of this workshop the student should be able to:

·       Create a setup file to specify the libraries that will be used

·       Read in a hierarchical design

·       Partition a design’s hierarchy optimally for synthesis

·       Constrain a complex design for area and timing, taking into account different environmental attributes such as output loading, input drive strength, process, voltage and temperature variations, as well as post-layout effects such as clock skew and net parasiticsy

·       Select the appropriate compile flow for your project

·       Execute the recommended synthesis techniques within each compile flow to achieve area and timing closures

·       Perform test-ready synthesis when appropriate

·       Write DC-Tcl scripts to constrain and compile designs

·       Generate and interpret timing, constraints and other debugging reports

·       Understand the effect that RTL coding style can have on synthesis results

·       Generate output data (netlist, timing/are constraints, physical constraints scan-def) that works with downstream physical design or layout tools

AUDIENCE PROFILE

ASIC digital designers who are going to use Design Compiler to synthesize Verilog or VHDL RTL modules to generate gate-level netlists.

PREREQUISITES

To benefit the most from the material presented in this workshop, you should:

·       Understand the functionality of digital sequential and combinational logic

·       Have familiarity with UNIX and a UNIX text editor of your choice

·       No prior Design Compiler knowledge or experience is needed

COURSE OUTLINE

Day 1

·       Introduction to Synthesis

·       Setting Up and Saving Designs

·       Design and Library Objects

·       Partitioning for Synthesis

·       Area and Timing Constraints

Day 2

·       Environmental Attributes

·       Compile Commands

·       Timing Analysis

·       More Constraint Considerations

·       Multiple Clock/Cycle Designs (Lecture)

Day 3

·       Multiple Clock/Cycle Designs (Lab)

·       Synthesis techniques and Flows

·       Integrated Design-for-Test

·       Pre- and Post-Synthesis Considerations

·       Conclusion

SYNOPSYS TOOLS USED

·       Design Compiler 2007.03

讲    师：Synopsys公司资深工程师

培训时间：2007年11月14日—16日9：00—17：00

培训地点：北京市海淀区知春路27号量子芯座5层培训中心

培训费用：人民币800元/人/天（含培训费、实验费、教材费、午餐）。

报名电话：82351166/87239511（移动）     传真：82357178

E－mail ：ictrain@bjicpark.com          网址：www.bjicpark.com

交费地点：北京市海淀区知春路27号量子芯座5层北京集成电路设计园培训中心

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请于开课前提前5个工作日将报名回执传真或Email至设计园，提前2个工作日将培训费用（现金、支票、汇款均可）交到设计园。
单位名称：北京集成电路设计园有限责任公司
开户银行：招商银行大运村支行
银行帐号：6381001510001
行    号：649