“SystemVerilog Assertions”培训课程

北京集成电路设计园与Synopsys公司将于2008年3月10日-11日举办“SystemVerilog Assertions”培训课程，以帮助IC工程师进一步全面系统地理解IC设计概念与方法。培训将采用Synopsys公司相关领域的培训教材，并由Synopsys公司资深工程师主讲，培训方式以讲课和实验穿插进行，保证足够的上机时间。

以下是课程介绍

SystemVerilog Assertions

OVERVIEW

In this workshop, you will be able to learn what assertion based verification is and how to implement assertions in your DUT with SystemVerilog. You will also learn SystemVerilog language basics for assertion and how to develop a testbench with SystemVerilog assertions.

After completing the course, you should have developed the skills to add SystemVerilog Assertions to your design, either from the Checker Library or written from scratch.

OBJECTIVES

At the end of the course you should be able to:

• Instantiate appropriate SVA in design source

• Use assertion library and assertion IP

• Compile, run &debug testbench with SystemVerilog assertions

• View SystemVerilog assertions result

• Build assertion structures based on properties and sequences

• Analysis assertion coverage result

AUDIENCE PROFILE

Design or Verification engineers writing assertion based testbenches to verify RTL code.

PREREQUISITES

To benefit the most from the material presented in this workshop, students should: Know Verilog and the VCS simulator, have basic programming skill and debugging experience with Verilog.

COURSE OUTLINE

    * Introduction to assertions

    * SVA checker library

    * Use Model and debug flow using DVE

    * Basic SVA constructs

    * Temporal behavior, Data Consistency

    * Coverage, Coding Guidelines

SYNOPSYS TOOLS USED

VCS 2006.06-SP1

讲    师：Synopsys公司资深工程师

培训时间：2008年3月10日—11日9：00—17：00

培训地点：海淀区科学院南路2号融科资讯中心A座7层711室（新思科技公司）

培训费用：人民币1000元/人/天（含培训费、实验费、教材费、午餐）

采用现金、支票、汇款支付均可。

报名电话：82351166/87239511（移动）     传真：82357178

E－mail ：ictrain@bjicpark.com          网址：www.bjicpark.com

交费地点：北京市海淀区知春路27号量子芯座5层北京集成电路设计园培训中心

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请于开课前提前5个工作日将报名回执传真或Email至设计园，提前2个工作日将培训费用（现金、支票、汇款均可）交到设计园。
单位名称：北京集成电路设计园有限责任公司
开户银行：招商银行大运村支行
银行帐号：6381001510001
行    号：649