Design Compiler 1培训课程+“免费机时”

    新思科技公司（Synopsys）将于2006年6月20日-22日举办“Design Compiler 1” 培训课程，以帮助IC工程师进一步全面系统地理解IC设计概念与方法。培训将采用Synopsys公司相关领域的培训教材，并由Synopsys公司资深工程师主讲，培训方式以讲课和实验穿插进行，保证一人一机及足够的上机时间。同时通知您北京集成电路设计园最新推出的优惠措施，即凡是在设计园全额缴费参加这两期培训的学员，可以额外免费享受设计园EDA平台10个小时的上机时间。在校学生凭学生证可获得5折优惠，5人以上一起报名可获得4折优惠。在校学生以7折价格参加培训的，可以免费享受5个小时上机时间（价值300元以上）。只要是设计园网站上公布的工具软件都可以使用，具体软件列表详见http://www.bjicpark.com/edarj.htm。使用时间是周一至周五的9：00——16：30，请提前1个工作日预约，预约电话：87239511。欢迎报名！以上培训内容介绍：

Introduction to Design Compiler 1：

OVERVIEW

This workshop will take you through the ASIC Synthesis design process starting from reading an HDL description into Design Compiler in XG mode, to generating a gate-level netlist ready for chip level integration. The workshop shows strategies for creating a design that meets timing requirements by observing HDL coding guidelines, properly constraining a design, partitioning the design for synthesis, and selecting the proper compile command options. This workshop also teaches designers to generate and interpret Design Compiler timing and design rule reports. Both Verilog and VHDL examples are used.

OBJECTIVES

 At the end of this workshop the student should be able to:

• List the steps involved in synthesizing an HDL design description
• Create a Design Compiler setup file
• Explain the effect of excessive hierarchy on synthesis results
• Anticipate the circuit structures likely to result from basic HDL coding constructs and recognize constructs that may reduce circuit quality
• Constrain and compile a simple* design for timing, area and design rules
• Constrain and compile a simple* design for different voltage and temperature variations
• Constrain and compile a simple* design, anticipating post-layout effects such as clock skew and net parasitics
• Generate and interpret timing and design rule reports of a simple* design
• Write Design Compiler Tcl scripts to constrain and compile simple* designs
• List the three levels of under-the-hood optimization performed by Design Compiler
• List several default behaviors of Design Compiler
• Explain how, when and why to use non-default options of Design Compiler
• Compile simple* designs top-down or using ACS and understand the advantages and disadvantages of each methodology

* A "simple" design is a synchronous, pre-layout design containing no clock dividers, tristate drivers or I/O pads.

AUDIENCE PROFILE

ASIC digital designers who are going to use Design Compiler to synthesize Verilog or VHDL RTL modules to generate gate-level netlists.

PREREQUISITES

 To benefit the most from the material presented in this workshop, you should:

• Have basic Verilog or VHDL knowledge
• Have familiarity with UNIX and a UNIX text editor of your choice

COURSE OUTLINE

 Day 1

• Introduction to Synthesis
• Setup, Libraries, and Objects
• Partitioning for Synthesis
• DC Tcl – An Introduction

Day 2

• Timing and Area
• Environmental Attributes
• Design Rules and Min Timing
• Timing Analysis

Day 3

• Multiple Clock/Cycle Designs
• Compile Strategies, Top-Down and ACS
• Before, During and After Synthesis
• Conclusion

讲    师：Synopsys公司资深工程师

培训时间：2006年6月20日-22日9：00—18：00

培训地点：海淀区科学院南路2号融科资讯中心A座7层711室（新思科技公司）

培训费用：人民币800元/人/天（含培训费、实验费、教材费、午餐），参加系列培训可享受优惠，采用现金、支票、汇款支付均可。在校学生可获得5折优惠（活动期间）。

交费地点：北京市海淀区知春路27号量子芯座5层北京集成电路设计园培训中心

联 系 人：邢老师

联系电话：87239511
传    真：82357178
E－mail ：xf@bjicpark.com

由于名额有限，请于开课前10天将报名回执传真或Email至设计园，并在得到确认以后将培训费用交到设计园。

报 名 回 执

公司名称：

参加课程：

参加人员：

1、姓名：               联系电话：                   Email：

2、姓名：               联系电话：                   Email：

3、姓名：               联系电话：                   Email：

请于开课前10天将报名回执传真或Email至设计园，并在得到确认以后将培训费用（现金、支票、汇款均可）交到设计园。

单位名称：北京集成电路设计园有限责任公司

开户银行：招商银行大运村支行

银行帐号：6381001510001

行　　号：649

传真：82357178     Email：xf@bjicpark.com

交费地点：北京市海淀区知春路27号量子芯座5层

北京集成电路设计园培训中心