TetraMAX 1 培训课程+“免费机时”

北京集成电路设计园与Synopsys公司将于2006年7月26日-27日举办“TetraMAX 1”培训课程，以帮助IC工程师进一步全面系统地理解IC设计概念与方法。培训将采用Synopsys公司相关领域的培训教材，并由Synopsys公司资深工程师主讲，培训方式以讲课和实验穿插进行，保证一人一机及足够的上机时间，并按要求完成所有的实验操作，培训结束颁发培训证书。

同时通知您设计园最新推出的优惠措施，即凡是在设计园全额缴费参加本期培训的学员，可以额外免费享受设计园EDA平台10个小时的上机时间。在校学生凭学生证可获得5折优惠，5人以上一起报名可获得4折优惠。在校学生以7折价格参加培训的，可以免费享受5个小时上机时间（价值300元以上）。设计园网站上公布的工具软件都可以使用，具体软件列表详见http://www.bjicpark.com/edarj.htm。使用时间是周一至周五的9：00——16：30，请提前1个工作日预约，预约电话：87239511。欢迎报名！本次培训内容介绍：

OVERVIEW

In this two-day workshop, you will learn how use TetraMAX®--Synopsys' ATPG Tool for SOC design--to perform the following tasks:

• Generate test patterns for stuck-at faults given a scan gate-level design created by DFT Compiler or other tools
• Describe the test protocol and test pattern timing using STIL
• Debug DRC and stuck-at fault coverage problems using the Graphical Schematic Viewer
• Troubleshoot fault coverage problems
• Save and validate test patterns

This class does NOT cover the fundamentals of manufacturing test, such as:

• What is manufacturing test?
• Why perform manufacturing test?
• What is a stuck-at fault?
• What is a scan chain?

This class covers in part the DSMTest option and the Failure Diagnosis feature of TetraMAX®.

OBJECTIVES

At the end of this workshop the student should be able to:

• Incorporate TetraMAX® ATPG in a design and test methodology that produces desired fault coverage, ATPG vector count and ATPG run-time for a full-scan or almost full-scan design
• Create a STIL Test Protocol File for a design by using QuickSTIL menus or commands, DFT Compiler or from scratch
• Use the Graphical Schematic Viewer to analyze and debug warning messages from Design Rule Check or fault coverage problems after ATPG
• Customize a Test Protocol for a design that requires special circuit initialization, scan shift or capture procedures or pattern timing
• Describe when and how to use at least four options to increase test coverage and/or decrease the number of required test patterns
• Save test patterns in a proper format for simulation and transfer to an ATE
• Validate test patterns using STIL Direct Pattern Validation

AUDIENCE PROFILE

ASIC, SoC or Test Engineers who perform ATPG at the Chip or SoC level

PREREQUISITES

To benefit the most from the material presented in this workshop, students should: Have taken the DFT Compiler 1 workshop or possess equivalent knowledge with DFT Compiler and fundamentals of manufacturing test including:

• Understanding the differences between manufacturing and design verification testing
• Stuck-at fault model
• Internal and boundary scan chains
• Scan shift and capture violations
• Major scan design-for-test rules concerning flip-flops, latches and bi-directional/tri-state drivers
• Tradeoffs between having single or multiple
• Understanding of digital IC logic design
• Working knowledge of Verilog or VHDL language
• Familiarity with UNIX workstations running X-windows
• Familiarity with vi, emacs, or other UNIX text editors

Students should make sure they are fully prepared to take this advanced material by conducting a self-assessment with the TetraMAX® 1 Prerequisite Test.

COURSE OUTLINE

Day 1

• Introduction to ATPG Test
• Building ATPG Models
• Running DRC
• Controlling ATPG

Day 2

• Minimizing ATPG Patterns
• Writing ATPG Patterns
• Pattern Validation
• DSM Testing Challenges
• Conclusion

SYNOPSYS TOOLS USED

TetraMAX® 2005.09-SP3
VCS 2005.06

讲    师：洪波，现为Synopsys技术支持中心资深应用工程师。主要负责为客户解决在芯片设计中遇到的综合、时序收敛、可测试设计和低功耗设计等问题。       

证    书：培训结束成绩合格者颁发Synopsys公司签发的结业证书

培训时间：2006年7月26日—27日9：00—17：00

培训地点：北京市海淀区知春路27号量子芯座5层培训教室

培训费用：人民币800元/人/天（含培训费、实验费、教材费、午餐），参加系列培训可享受优惠，采用现金、支票、汇款支付均可。在校学生可获得5折优惠（活动期间）。

交费地点：北京市海淀区知春路27号量子芯座5层北京集成电路设计园培训中心

联 系 人：邢老师

联系电话：87239511
传    真：82357178
E－mail ：xf@bjicpark.com

请于开课前提前5个工作日将报名回执传真或Email至设计园，并请在开课前提前1个工作日将培训费用交到设计园。

报 名 回 执

公司名称：

参加课程：

参加人员：

1、姓名：               联系电话：                   Email：

2、姓名：               联系电话：                   Email：

3、姓名：               联系电话：                   Email：

请于开课前提前5个工作日将报名回执传真或Email至设计园，并请在开课前提前1个工作日将培训费用（现金、支票、汇款均可）交到设计园。

单位名称：北京集成电路设计园有限责任公司

开户银行：招商银行大运村支行

银行帐号：6381001510001

行　　号：649

传真：82357178     Email：xf@bjicpark.com

交费地点：北京市海淀区知春路27号量子芯座5层

北京集成电路设计园培训中心