Chip Sythesis training course

Overview

This workshop will go through the ASIC Synthesis design process starting from reading an HDL description into Design Compiler, to generating a gate-level netlist ready for chip level integration. The workshop shows strategies for creating a design that meets timing requirements by observing HDL coding guidelines, properly constraining a design, partitioning the design for synthesis, and selecting the proper compile command options. This workshop also teaches designers to generate and interpret Design Compiler timing and design rule reports. Both Verilog and VHDL examples are used.
Objectives
At the end of this workshop the student should be able to:
　　List the steps involved in synthesizing an HDL design description
　　Create a Design Compiler setup file
　　Explain the effect of excessive hierarchy on synthesis results
　　Anticipate the circuit structures likely to result from basic HDL coding constructs 　　and recognize constructs that may reduce circuit quality
　　Constrain and compile a simple* design for timing, area and design rules
　　Constrain and compile a simple* design for different voltage and temperature 　　　　　variations
　　Constrain and compile a simple* design, anticipating post-layout effects such as 　　　clock skew and net parasitics
　　Generate and interpret timing and design rule reports of a simple* design
　　Write Design Compiler Tcl scripts to constrain and compile simple* designs
　　List the three levels of under-the-hood optimization performed by Design Compiler
　　List several default behaviors of Design Compiler
　　Explain how, when and why to use non-default options of Design Compiler
　　Compile a simple design containing multiple instances of a cell
　　Compile simple designs top-down and bottom-up and understand the advantages and 　　　disadvantages of each methodology
* A "simple" design is a synchronous, pre-layout design containing no clock dividers, tristate drivers or I/O pads.
Audience Profile
ASIC digital designers who are going to use Design Compiler to synthesize Verilog or VHDL RTL module to generate gate-level netlist.
Prerequisites
To benefit the most from the material presented in this workshop, students should:
　　Have basic Verilog or VHDL knowledge
　　Have familiarity with UNIX and its text editor
Hands-On Labs
Each day will include hands-on labs to reinforce the topics covered during the lecture. Some of the labs extend beyond the lecture to covered on tasks that most appropriate during hand-on exercise like navigating the graphical user interface (GUI). Designers will gain experience in:
　　Writing efficient HDL (Verilog or VHDL) for synthesis
　　Partitioning the design for optimal synthesis results
　　Effectively using Design Analyzer
　　Performing static timing analysis
　　Properly constraining the design
　　Working with designs that has multiple instantiations
　　Performing top-down compiler strategy
　　Improving the timing and area of the design through optimization techniques
　　Using DesignWare MacroCell through coreConsultant
　　Properly setting up DC initialization files
　　Writing effective scripts in Tcl
　　Resolving problems with the optimization of the design
　　Executing RTL synthesis flow
Synopsys Tools Used
　　Design Compiler Family
　　Design Analyzer
　　DesignWare coreConsultant