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“Virtuoso
Analog Design Environment”培训课程
北京集成电路设计园与Cadence公司将于2008年3月26日-28日举办“Virtuoso
Analog Design Environment”培训课程，以帮助IC工程师进一步全面系统地理解IC设计概念与方法。培训将采用Cadence公司相关领域的培训教材，并由Cadence公司资深工程师主讲，培训方式以讲课和实验穿插进行，保证一人一机及足够的上机时间，并按要求完成所有的实验操作，培训结束颁发培训证书。
以下是课程介绍：
Description:
By
taking this course, you'll learn front-to-back design flow with the
Virtuoso® Analog Design Environment system. You will start with a
top-level block description of your design, build schematics, run
simulations, and utilize the entire Virtuoso Analog Design
Environment.
By
using a series of simulation tools, you will verify circuit
operation over process corners, optimize component values, and
accurately predict production yield. Afterwards, you will learn to
use the environment to write and then execute automated simulation
runs, finishing the design flow with layout parasitic extraction and
simulation.
Learning Objectives:
Upon
completion of this course, the student will be able to:
Use
the Cadence® Design Framework II environment
Simulate circuits with the Virtuoso® Spectre Circuit Simulator
Run
analog behavioral (AHDL) simulations with the Verilog®-A simulator
Capture a schematic of a BiCMOS amplifier with the Virtuoso®
Schematic Editor
Use
the Schematic Editor Symbol Generator to create symbols for your
schematics
Netlist and simulate a BiCMOS amplifier
Analyze simulation results with the Waveform Window and the WaveScan
tool
Run
parametric analysis
Simulate over process corners using the Corners Analysis tool
Perform sensitivity analysis
Run
batch simulations with Open Command Environment for ANalysis (OCEAN)
Create
new components using the Component Description Format (CDF)
Simulate with ideal macromodels
Use
inline subcircuits to simulate components with parasitic models
Use
inherited connections to reprogram a wired connection by
instantiated property
Use
the Hierarchy Editor to configure a design hierarchy with different
cell views
Run
Monte Carlo and optimization analyses
Perform layout parasitic extraction and simulate the circuit with
parasitics
Software:
Virtuoso® Layout Editor
LVS
LPE
Verilog-A simulator
Virtuoso® Spectre Circuit Simulator
Virtuoso® Analog Circuit Optimizer Option
Virtuoso® Analog Corners Analysis Option
Virtuoso® Analog Design Environment
Cadence® Design Framework II
OCEAN
Virtuoso® Schematic Editor
Agenda:
Day 1
Introduction and design flow overview
Top-down simulation, including analog behavioral modeling
Capturing the schematic of a BiCMOS operational amplifier
Setting up the analog simulation environment
Running simulations with the Virtuoso® Spectre Direct simulator
Analyzing simulation results
Exploring the Waveform Window features
Using
the WaveScan Tool
Saving
and restoring simulation states
Annotating simulation results in the schematic
Day 2
Using
the Waveform Calculator to measure the simulation results
Backing up simulation data
Using
the Results Browser
Using
the Print Engine/Conditional Search tool
Exploring Virtuoso® Spectre sweep features
Using
OCEAN and SKILL
Running Virtuoso® Spectre MDL
Analyzing dcmatch, and transient operating point results
Using
the Component Description Format (CDF)
Running simulations with subcircuits and macromodels
Using
inline subcircuits
Set up
and run Parametric Analysis
Using
the Corners Analysis tool
Day 3
Running Monte Carlo Analysis
Exploring designs with the Optimization tool
Using
the Hierarchy Editor
Set up
and run parasitic extraction
Backannotate extracted parasitics to the schematic
Simulate the circuit with extracted parasitics
Using
Inherited Connections and other features of the Virtuoso Analog
Design Environment
Audience:
Analog/Mixed-Signal IC Designers
Analog
Designers
All
users of the Cadence Analog Design Environment (formerly Analog
Artist) 4.3x and 4.4x as well as Cadence Analog Design Environment
4.4.6 who have not yet used the WaveScan or SpectreMDL.
Special Notes:
Prerequisites:
Analog Schematics and Simulation
Design
methodology
Some
programming experience
UNIX
OS
You should already have knowledge of:
It is
assumed the student has a basic knowledge of analog circuit design
and terminology. It is highly recommended that the student is
familiar with basic UNIX commands. It is also recommended that the
student has some experience in the use of circuit simulators such as
SPICE.
讲
师：Cadence公司资深工程师
培训时间：2008年3月26日-28日9：00—17：00
培训地点：北京市海淀区知春路27号量子芯座5层培训中心
培训费用：人民币800元/人/天（含培训费、实验费、教材费、午餐）；
采用现金、支票、汇款支付均可。
报名电话：82351166
传真：82357178
E－mail
：ictrain@bjicpark.com
网址：www.bjicpark.com
交费地点：北京市海淀区知春路27号量子芯座5层北京集成电路设计园培训中心
报名回执下载
请于开课前提前10个工作日将报名回执传真或Email至设计园，提前2个工作日将培训费用（现金、支票、汇款均可）交到设计园。
单位名称：北京集成电路设计园有限责任公司
开户银行：招商银行大运村支行
银行帐号：6381001510001
行
号：649
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