北京集成电路设计园与Cadence公司将于2008年4月24日-25日举办“Low-Power Implementation”培训课程，以帮助IC工程师进一步全面系统地理解IC设计概念与方法。培训将采用Cadence公司相关领域的培训教材，并由Cadence公司资深工程师主讲，培训方式以讲课和实验穿插进行，保证一人一机及足够的上机时间，并按要求完成所有的实验操作，培训结束颁发培训证书。

以下是课程介绍：

Description:

This is an Engineer Explorer class for designers familiar with digital implementation using the Encounter® platform.

In this course, you explore and implement several low-power techniques to reduce both dynamic and leakage power during synthesis and design implementation. You run formal verification to ensure the functionality of the low-power design.

Learning Objectives:

 In this course, you Create and use the Si2 Common Power Format file to specify the power intent of your design. Set up and run synthesis directives and constraints to reduce dynamic and leakage power Implement multi-supply voltage (MSV) regions to reduce power consumption Implement a low-power clock tree Run concurrent timing, MSV optimization, and multi-Vt (leakage) optimization Implement MSV-aware detail routing

Run sign-off power analysis with VoltageStorm® software to display the IR drop in your design. Verify the design implementation by running low-power formal verification Analyze data and debug power problems at different stages of the flow

Software: SoC Encounter™ XL

Encounter® Conformal® Low Power XL

Agenda:

Day 1

Creating power specifications using the Common Power Format file

Exploring active and leakage power reduction concepts

Reducing active or dynamic power during synthesis

Optimizing for leakage power in synthesis

Day 2

Running multi-supply voltage synthesis

Implementing multi-supply voltage

Optimizing leakage power during implementation

Exploring the effective current source model

Applying power sign-off considerations

Audience: Digital IC Designers

Chip Designers

ASIC Designers

Prerequisites: You need to have taken the Floorplanning and Physical Synthesis with First Encounter® XL course (formerly known as First Encounter XL) and to have practical experience in Design methodology Place and route The SoC Encounter™ platform

讲    师：Cadence公司资深工程师

培训时间：2008年4月24日-25日9：00—17：00

培训地点：北京市海淀区知春路27号量子芯座5层培训中心

培训费用：人民币800元/人/天（含培训费、实验费、教材费、午餐）；

采用现金、支票、汇款支付均可。

报名电话：82351166                        传真：82357178

E－mail ：ictrain@bjicpark.com            网址：www.bjicpark.com

交费地点：北京市海淀区知春路27号量子芯座5层北京集成电路设计园培训中心

报名回执下载

请于开课前提前10个工作日将报名回执传真或Email至设计园，提前2个工作日将培训费用（现金、支票、汇款均可）交到设计园。
单位名称：北京集成电路设计园有限责任公司
开户银行：招商银行大运村支行
银行帐号：6381001510001
行      号：649