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ConvergenSC ”
培训课程
北京集成电路设计园与CoWare公司于2008年6月4日-6日共同举办“ConvergenSC”培训课程，以帮助IC系统级设计工程师进一步全面理解系统级设计概念和方法。课程将采用相关领域的培训教材，由CoWare资深工程师主讲。培训方式以讲课和实验穿插进行，保证一人一机及足够的上机时间，并按要求完成所有的实验操作。
以下是课程介绍：
OVERVIEW
In this intensive, three-day course, you will learn the key features，benefits and usage of ConvergenSC
Platform Architect. This course is a workshop that teaches system
engineers how to build a powerful environment to quickly assemble,
configure and optimize SoC platforms at the transaction level in
SystemC, do the best-in-class architectural and performance
analysis, import and integrate VHDL and Verilog blocks with a
SystemC transaction level system to do co-simulation. The strategies
for creating a SoC system, analyzing the bus, processor, memory and
software running, and properly partitioning of the whole SoC design
will be show in this workshop. Two popular system-level design
methodologies: top-down design and platform-based design are
supported by the ConvergenSC Platform Architect
OBJECTIVES
At the end of this workshop the student
should be able to:
Build, run and debug
SystemC simulations in both command line interface and SystemC IDE
environment Control the build process through the use of TCL and
Makefiles Modeling with SystemC TLM and using TLM application
programming interface Import SystemC modules or HDL modules and save
them as system libraries Create a SoC platform by using system IP
libraries in both Platform-based design flow and top-down design
flow Create and attach monitors to connections for tracing of
communication Use CoWare SystemC analysis libraries for
Instrumenting own IPs to gain analysis functions Use CoWare analysis
methodologies and analysis functions to analyze bus, processor,
memory and software to get the architecture right before
implementation begins Build and run SystemC and Verilog/VHDL
co-simulation
AUDIENCE PROFILE
System, SoC, IC designers
who are going to use SystemC to modeling own IPs, system, going to
validate SoC architecture/HW/SW by creating and analyzing virtual
SoC platform to gain the right performance.
PREREQUISITES
To benefit the most from the material
presented in this workshop, you should:
Have basic SystemC Knowledge
Have basic Verilog or VHDL knowledge
Have familiarity with UNIX and a UNIX text
editor of your choice
COURSE OUTLINE
Day1
Introduction
Simulation and SystemVerifier (CLI)
The
Build Environment (Makefiles)
Simulation and SystemC IDE (Eclipse)
TLM
Day2
System
Level Design Overview
Working
with Libraries
Platform-based Design
Top-Down Design
System
Level Topic
Day3
Using
Analysis
Analysis Libraries
Analysis Case Studies
Performing HDL Co-simulation
Writing Proxy Modules
讲 师：CoWare公司资深工程师
培训时间：2008年6月4日-6日9：00—17：00
培训地点：北京市海淀区知春路27号量子芯座5层培训中心
培训费用：人民币800元/人/天（含培训费、实验费、教材费、午餐）；
采用现金、支票、汇款支付均可。
报名电话：82351166
传真：82357178
E－mail
：ictrain@bjicpark.com
网址：www.bjicpark.com
报名回执下载
交费地点：北京市海淀区知春路27号量子芯座5层北京集成电路设计园培训中心
请于开课前提前10个工作日将报名回执传真或Email至设计园，提前2个工作日将培训费用（现金、支票、汇款均可）交到设计园。
单位名称：北京集成电路设计园有限责任公司
开户银行：招商银行大运村支行
银行帐号：6381001510001
行 号：649
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