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“SystemVerilog Testbench
”
培训课程
北京集成电路设计园与Synopsys公司将于2008年3月19日-21日举办“SystemVerilog Testbench”培训课程，以帮助IC工程师进一步全面系统地理解IC设计概念与方法。培训将采用Synopsys公司相关领域的培训教材，并由Synopsys公司资深工程师主讲，培训方式以讲课和实验穿插进行，保证一人一机及足够的上机时间，并按要求完成所有的实验操作，培训结束颁发培训证书。
SystemVerilog Testbench
OVERVIEW
In this hands-on workshop,
you will learn SystemVerilog language basics
and how to develop a
testbench using SystemVerilog. With help of this
course,
you will be able to know how to compile, run, debug and analysis
a SystemVerilog simulation,
how random stimulus is generated, how to write basic
transactors,
how to define coverage group and most importantly, how to analysis
the coverage result.
After completing the course, you should have
developed the skills to write a SystemVerilog testbench to verify
Verilog/SystemVerilog RTL code with coverage-driven random stimulus.
OBJECTIVES
At the end of the course you should be able to:
· Develop an
SystemVerilog verification environment
· Handle
SystemVerilog language basic
· Understand
concurrency thread concept and how to manage interthread
communication
· Understand how
to maximum code reusability with help of SystemVerilog
OOP feature
· Build
randomization stimulus generator
· Implement
function coverage group
AUDIENCE PROFILE
Design or Verification engineers writing SystemVerilog testbenches
to
verify Verilog or SystemVerilog code.
PREREQUISITES
To benefit
the
most
from the
material
presented
in this workshop,
studentts should:
Familiarity with a UNIX test editor
Have basic programming skill and
debugging experience with Verilog, VHDL or C
COURSE OUTLINE
Day 1
· The Device Under Test
· SystemVerilog Verification Environment
· SystemVerilog Language Basics
· Drive and Sample DUT Signals
Day 2
· Concurrency
· Object Oriented Programming (OOP) -
Encapsulation
· Object Oriented Programming (OOP) –
Randomization
Day 3
· Object Oriented Programming (OOP) – Inheritance
· Inter-Thread Communications
· Functional Coverage
· SystemVerilog VMM Preview
SYNOPSYS TOOLS USED
VCS 2006.06-SP1
讲 师：Synopsys公司资深工程师
培训时间：2008年3月19日—21日9：00—17：00
培训地点：北京市海淀区知春路27号量子芯座5层培训中心
培训费用：人民币1000元/人/天（含培训费、实验费、教材费、午餐）；
采用现金、支票、汇款支付均可。
报名电话：82351166
传真：82357178
E－mail ：ictrain@bjicpark.com
网址：www.bjicpark.com
交费地点：北京市海淀区知春路27号量子芯座5层北京集成电路设计园培训中心
报 名 回 执 下 载
请于开课前提前5－10个工作日将报名回执传真或Email至设计园，提前2个工作日将培训费用（现金、支票、汇款均可）交到设计园。
单位名称：北京集成电路设计园有限责任公司
开户银行：招商银行大运村支行
银行帐号：6381001510001
行 号：649
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