北京集成电路设计园

Be One Lab Functional Verification Methodology and Flow培训班

　　北京集成电路设计园与天一集成电路设计(深圳)有限公司联合举办的Functional Verification Methodology and Flow培训班，课程范围涉及业界领先的验证方法学、规范化的验证流程、验证EDA 工具箱的简要分类介绍及实际使用知识、如何搭建高效可重复使用的Test Bench 以及通过以往成功案例来分析项目难度评估及管理措施等，还会对您在当前项目验证上的疑虑提供专业咨询与解答。本课程将由Be One Lab 资深专家采用中英文讲授。
主讲人简介：
Issac Lian 是天一集成电路设计有限公司的发起人、总裁。天一致力于ASIC/FPGA设计服务，在深圳、多伦多、加州均设有办公室。Mr.Lian 曾帮助阿尔卡特、亿恒科技、华为等公司实现过多片"One-Passed "复杂芯片设计。他还是Verisity 公司的Specmane 语言培训师，曾为阿尔卡特、英特尔、德州仪器等公司培训专业人员。Mr.Lian 拥有滑铁卢大学电子工程硕士、电子工程学士和物理学士学位。
学员需预备以下基础知识:

熟悉UNIX 操作系统及通用的文本编辑器
对数字逻辑设计有基本了解

课程收费: 600 元（包括培训费、证书、午餐及茶歇）
时间 :2002 年12 月16 -17 日
地点 :北京集成电路设计园培训中心
主讲 :Issac Lian /Valentine Jing
证书 :课程结束后颁发"B1Lab Functional Verification Methodology and Flow " 结业证书
课程安排
Day 1:

What is functional verification and what is being verified　
Formal Verification,Equivalence Checking,Model checking,
Functional Verification,Test Bench Generation
Functional Verification Approaches
Black-Box,White-Box,Grey-Box
The Verification Process
Specification and Test Plan ((Specification->Features->Test cases)
Direct 、Direct-Random and Random Test Case
Advanced Verification Methodology
System//Chip/Module Level Verification
Behavioral Hardware Description Languages
Stimulus and Response
Generating complex waveforms,Self-Checking test benches,Complex
Response,Predicting the output
How to build reusable test bench
Test Bench Acceleration
Coverage Analysis in the Design Flow
Feature Coverage and Code Coverage (Line Condition Toggle FSM)
Coding Guidelines
Structure,Naming Convention,Comments,Syntax,Debugging
Simulation Management
Modeling reset,Writing Good Behavioral Model,Regression Management

Day 2

Assertions Methodology
Formal Verification ((Design Rule Check)
Vector--based Verification
Memory Verification
Project Management and Verification Experience
Introduce the useful verification experience that have been
successfully used to produce one-passed ASICs,SoC,board,and
entire systems.
Verisity 's Specman e language
Verisity 's e VC(e Verification Component)
Verisity 's e RM(e Reuse Methodlogy)